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PRELIMINARY
CY28447
Clock Generator for Intel(R) Calistoga Chipset
Features
* Compliant to Intel(R) CK410M * Selectable CPU frequencies * Differential CPU clock pairs * 100 MHz differential SRC clocks * 96 MHz differential dot clock * 27 MHz Spread and Non-spread video clock * 48 MHz USB clock * SRC clocks independently stoppable through CLKREQ#[1:9] * 96/100 MHz spreadable differential video clock
CPU x2 / x3 SRC x9/11 PCI x5 REF x2 DOT96 x1 USB_48M x1 LCD x1 27M x2
* 33 MHz PCI clocks * Buffered Reference Clock 14.318MHz * Low-voltage frequency select inputs * I2C support with readback capabilities * Ideal Lexmark Spread Spectrum profile for maximum electromagnetic interference (EMI) reduction * 3.3V power supply * 72-pin QFN package
Block Diagram
XIN XOUT SEL_CLKREQ PCI_STP# CPU_STP# CLKREQ[1:9]# ITP_SEL FS[C:A] 14.318M Hz Crystal VDD REF[1:0] IREF VDD CPUT[0:1] CPUC[0:1] VDD CPUT2_ITP/SRCT10 CPUC2_ITP/SRCC10 VDD SRCT(1:9]) SRCC(1:9]) VDD PCI[1:4] VDD_PCI PCIF0 VDD SRCT0/100M T_SST SRCC0/100M C_SST VDD48 27MSpread VDD48 DOT96T DOT96C VDD48 48M 27M PLL VTT_PW RGD#/PD SDATA SCLK I2C Logic
Pin Configuration
CLKREQ9# CLKREQ8# SRCT_8 SRCC_8 VSS_SRC SRCC_7 SRCT_7 VDD_SRC SRCC_6 SRCT_6 CLKREQ6# SCRC_5 SRCT_5 SCRC_4 SRCT_4 CLKREQ4# SRCC_3 SRCT_3
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55
PLL Reference
CPU PLL
Divider
LVDS PLL FCTSEL1
Divider
VDD_SRC SRCC_9 SRCT_9 VSS_SRC CPUC2_ITP / SRCC_10 CPUT2_ITP / SRCT_10 VDDA VSSA IREF CPUC1 CPUT1 VDD_CPU CPUC0 CPUT0 VSS_CPU SCLK SDATA VDD_REF
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
54 53 52 51 50 49 48 47
CY28447
46 45 44 43 42 41 40 39 38 37
VDD_SRC SRCC_2 SRCT_2 SRCC_1 SRCT_1 VDD_SRC SRCC_0 / LCD100MC SRCT_0 / LCD100MT CLKREQ1# FSB/TEST_MODE DOT96C / 27M_SS DOT96T / 27M_NSS VSS_48 48M / FSA VDD_48 VTT_PWRGD# / PD CLKREQ7# PCIF0/ITP_SEL
Divider
Divider
VDD48 27MNon-spread
Rev 1.0, November 20, 2006
2200 Laurelwood Road, Santa Clara, CA 95054 Tel:(408) 855-0555 Fax:(408) 855-0550
XOUT XIN VSS_REF REF1 REF0 / FSC_TEST_SEL CPU_STP# PCI_STP# CLKREQ2# PCI1 CLKREQ3# CLKREQ5# VDD_PCI VSS_PCI PCI2 PCI3 PCI4 / FCTSEL1 VSS_PCI VDD_PCI
Fixed PLL
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CY28447
Pin Description
Pin No. 2, 3, 50, 51, 52, 53, 55, 56, 58, 59, 60, 61, 63, 64, 66, 67, 69, 70 4, 68 5, 6 Name SRCT/C[1:9] Type PWR 3.3V power supply for outputs. Description 1, 49, 54, 65 VDD_SRC
O, DIF 100 MHz Differential serial reference clocks.
VSS_SRC
GND
Ground for outputs.
CPUT2_ITP/SRCT10, O, DIF Selectable differential CPU or SRC clock output. CPUC2_ITP/SRCC10 ITP_SEL = 0 @ VTT_PWRGD# assertion = SRC10 ITP_SEL = 1 @ VTT_PWRGD# assertion = CPU2 VDDA VSSA IREF PWR GND I 3.3V power supply for PLL. Ground for PLL. A precision resistor is attached to this pin which is connected to the internal current reference. 3.3V power supply for outputs. Ground for outputs. SMBus-compatible SCLOCK. 3.3V power supply for outputs. 14.318 MHz crystal input. Ground for outputs. Fixed 14.318 MHz clock output.
7 8 9
10, 11, 13, 14 CPUT/C[0:1] 12 15 16 17 18 19 20 21 22 23 VDD_CPU VSS_CPU SCLK SDATA VDD_REF XOUT XIN VSS_REF REF1
O, DIF Differential CPU clock outputs. PWR GND I PWR I GND O
I/O, OD SMBus-compatible SDATA. O, SE 14.318 MHz crystal output.
REF0/FSC_TESTSEL I/O,PD Fixed 14.318 clock output / 3.3V-tolerant input for CPU frequency selection/Selects test mode if pulled to VIMFS_C when VTT_PWRGD# is asserted LOW. Refer to DC Electrical Specifications table for VILFS_C,VIMFS_C,VIHFS_C specifications. CPU_STP# PCI_STP# CLKREQ[1:9]# I, PU I, PU I, PU 3.3V LVTTL input for CPU_STP# active LOW. 3.3V LVTTL input for PCI_STP# active LOW. 3.3V LVTTL input for enabling assigned SRC clock (active LOW).
24 25 26, 28, 29, 38, 46, 57, 62, 71, 72 27, 32, 33 30, 36 31, 35 34
PCI[1:3] VDD_PCI VSS_PCI PCI4/FCTSEL1
O, SE 33 MHz clock outputs PWR GND 3.3V power supply for outputs. Ground for outputs.
I/O, PD 33 MHz clock output / 3.3V LVTTL input for selecting pins 47,48 (SRC[T/C]0, 100M[T/C]) and pins 43,44 (DOT96[T/C] and 27M Spread and Non-spread) (sampled on the VTT_PWRGD# assertion).
FCTS E L1 P in 43
0 DOT96T 1 27M_NSS
P in 44
DOT96C 27M_SS
P in 47
SRCT0
P in 48
SRCC0
96/100M_T 96/100M_C
37
ITP_SEL/PCIF0
I/O, PD, 3.3V LVTTL input to enable SRC10 or CPU2_ITP / 33-MHz clock output. SE (sampled on the VTT_PWRGD# assertion). 1 = CPU2_ITP, 0 = SRC10
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CY28447
Pin Description (continued)
Pin No. 39 Name VTT_PWRGD#/PD Type I, PD Description 3.3V LVTTL input. This pin is a level sensitive strobe used to latch the FSA, FSB, FSC, FCTSEL1, and ITP_SEL. After VTT_PWRGD# (active LOW) assertion, this pin becomes a real-time input for asserting power down (active HIGH). 3.3V power supply for outputs. Fixed 48-MHz clock output / 3.3V-tolerant input for CPU frequency selection Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications. Ground for outputs.
40 41 42 43, 44 45
VDD_48 48M/FSA VSS_48 DOT96T/ 27M_NSS DOT96C/ 27M_SS FSB/TEST_MODE
PWR I/O GND
O, DIF Fixed 96-MHz clock output or 27 Mhz Spread and Non-spread output Selected via FCTSEL1 at VTTPWRGD# assertion. I 3.3V-tolerant input for CPU frequency selection. Selects Ref/N or Tri-state when in test mode 0 = Tri-state, 1 = Ref/N Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
47, 48
SRC[T/C]0/ LCD100M[T/C]
O,DIF 100 MHz differential serial reference clock output / Differential 96/100-MHz SS clock for flat-panel display Selected via FCTSEL1 at VTTPWRGD# assertion. initialize to their default setting upon power-up, and therefore use of this interface is optional. Clock device register changes are normally made upon system initialization, if any are required. The interface cannot be used during system operation for power management functions.
Frequency Select Pins (FSA, FSB, and FSC)
Host clock frequency selection is achieved by applying the appropriate logic levels to FSA, FSB, FSC inputs prior to VTT_PWRGD# assertion (as seen by the clock synthesizer). Upon VTT_PWRGD# being sampled LOW by the clock chip (indicating processor VTT voltage is stable), the clock chip samples the FSA, FSB, and FSC input values. For all logic levels of FSA, FSB, and FSC, VTT_PWRGD# employs a one-shot functionality in that once a valid LOW on VTT_PWRGD# has been sampled, all further VTT_PWRGD#, FSA, FSB, and FSC transitions will be ignored, except in test mode.
Data Protocol
The clock driver serial protocol accepts byte write, byte read, block write, and block read operations from the controller. For block write/read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. For byte write and byte read operations, the system controller can access individually indexed bytes. The offset of the indexed byte is encoded in the command code, as described in Table 2. The block write and block read protocol is outlined in Table 3 while Table 4 outlines the corresponding byte write and byte read protocol. The slave receiver address is 11010010 (D2h)
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through the Serial Data Interface, various device functions, such as individual clock output buffers, can be individually enabled or disabled. The registers associated with the Serial Data Interface Table 1. Frequency Select Table FSA, FSB, and FSC[1] FSC 1 0 0 0
.
FSB 0 0 1 1
FSA 1 1 1 0
CPU 100 MHz 133 MHz 166 MHz 200 MHz
SRC 100 MHz 100 MHz 100 MHz 100 MHz
PCIF/PCI 33 MHz 33 MHz 33 MHz 33 MHz
27MHz 27 MHz 27 MHz 27 MHz 27 MHz
REF0 14.318 MHz 14.318 MHz 14.318 MHz 14.318 MHz
DOT96 96 MHz 96 MHz 96 MHz 96 MHz
USB 48 MHz 48 MHz 48 MHz 48 MHz
Table 2. Command Code Definition Bit 7 (6:0) Description 0 = Block read or block write operation, 1 = Byte read or byte write operation Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000'
Note: 1. 27-MHz and 96-MHz can not be output at the same time.
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Table 3. Block Read and Block Write Protocol Block Write Protocol Bit 1 8:2 9 10 18:11 19 27:20 28 36:29 37 45:38 46 .... .... .... .... Start Slave address - 7 bits Write Acknowledge from slave Command Code - 8 bits Acknowledge from slave Byte Count - 8 bits (Skip this step if I2C_EN bit set) Acknowledge from slave Data byte 1 - 8 bits Acknowledge from slave Data byte 2 - 8 bits Acknowledge from slave Data Byte/Slave Acknowledges Data Byte N - 8 bits Acknowledge from slave Stop Description Bit 1 8:2 9 10 18:11 19 20 27:21 28 29 37:30 38 46:39 47 55:48 56 .... .... .... .... Table 4. Byte Read and Byte Write Protocol Byte Write Protocol Bit 1 8:2 9 10 18:11 19 27:20 28 29 Start Slave address - 7 bits Write Acknowledge from slave Command Code - 8 bits Acknowledge from slave Data byte - 8 bits Acknowledge from slave Stop Description Bit 1 8:2 9 10 18:11 19 20 27:21 28 29 37:30 38 39 Start Slave address - 7 bits Write Acknowledge from slave Command Code - 8 bits Acknowledge from slave Repeated start Slave address - 7 bits Read Acknowledge from slave Data from slave - 8 bits NOT Acknowledge Stop Byte Read Protocol Description Start Slave address - 7 bits Write Acknowledge from slave Command Code - 8 bits Acknowledge from slave Repeat start Slave address - 7 bits Read = 1 Acknowledge from slave Byte Count from slave - 8 bits Acknowledge Data byte 1 from slave - 8 bits Acknowledge Data byte 2 from slave - 8 bits Acknowledge Data bytes from slave / Acknowledge Data Byte N from slave - 8 bits NOT Acknowledge Stop Block Read Protocol Description
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Control Registers
Byte 0: Control Register 0 Bit 7 6 5 4 3 2 1 0 @Pup 1 1 1 1 1 1 1 1 Name SRC[T/C]7 SRC[T/C]6 SRC[T/C]5 SRC[T/C]4 SRC[T/C]3 SRC[T/C]2 SRC[T/C]1 SRC[T/C]0 /LCD_96_100M[T/C] Description SRC[T/C]7 Output Enable 0 = Disable (Tri-state), 1 = Enable SRC[T/C]6 Output Enable 0 = Disable (Tri-state), 1 = Enable SRC[T/C]5 Output Enable 0 = Disable (Tri-state), 1 = Enable SRC[T/C]4 Output Enable 0 = Disable (Tri-state), 1 = Enable SRC[T/C]3 Output Enable 0 = Disable (Tri-state), 1 = Enable SRC[T/C]2 Output Enable 0 = Disable (Tri-state), 1 = Enable SRC[T/C]1 Output Enable 0 = Disable (Tri-state), 1 = Enable SRC[T/C]0 / LCD_96_100M[T/C] Output Enable 0 = Disable (Hi-Z), 1 = Enable
Byte 1: Control Register 1 Bit 7 6 5 4 3 2 1 0 @Pup 1 1 1 1 1 1 1 0 Name PCIF0 PCIF0 Output Enable 0 = Disabled, 1 = Enabled Description
27M NSS / DOT_96[T/C] 27M Non-spread and DOT_96 MHz Output Enable 0 = Disable (Tri-state), 1 = Enabled USB_48MHz REF0 REF1 CPU[T/C]1 CPU[T/C]0 CPU, SRC, PCI, PCIF Spread Enable USB_48M MHz Output Enable 0 = Disabled, 1 = Enabled REF0 Output Enable 0 = Disabled, 1 = Enabled REF1 Output Enable 0 = Disabled, 1 = Enabled CPU[T/C]1 Output Enable 0 = Disable (Tri-state), 1 = Enabled CPU[T/C]0 Output Enable 0 = Disable (Tri-state), 1 = Enabled PLL1 (CPU PLL) Spread Spectrum Enable 0 = Spread off, 1 = Spread on
Byte 2: Control Register 2 Bit 7 6 5 4 3 2 1 0 @Pup 1 1 1 1 1 1 1 1 Name PCI4 PCI3 PCI2 PCI1 Reserved Reserved CPU[T/C]2 Reserved PCI4 Output Enable 0 = Disabled, 1 = Enabled PCI3 Output Enable 0 = Disabled, 1 = Enabled PCI2 Output Enable 0 = Disabled, 1 = Enabled PCI1 Output Enable 0 = Disabled, 1 = Enabled Reserved, Set = 1 Reserved, Set = 1 CPU[T/C]2 Output Enable 0 = Disabled (Hi-Z), 1 = Enabled Reserved, Set = 1 Description
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Byte 3: Control Register 3 Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 0 0 0 Name SRC7 SRC6 SRC5 SRC4 SRC3 SRC2 SRC1 SRC0 Description Allow control of SRC[T/C]7 with assertion of PCI_STP# or SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# Allow control of SRC[T/C]6 with assertion of PCI_STP# or SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# Allow control of SRC[T/C]5 with assertion of PCI_STP# or SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# Allow control of SRC[T/C]4 with assertion of PCI_STP# or SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# Allow control of SRC[T/C]3 with assertion of PCI_STP# or SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# Allow control of SRC[T/C]2 with assertion of PCI_STP# or SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# Allow control of SRC[T/C]1 with assertion of PCI_STP# or SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# Allow control of SRC[T/C]0 with assertion of PCI_STP# or SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP#
Byte 4: Control Register 4 Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 1 1 1 Name LCD_96_100M[T/C] DOT96[T/C] RESERVED RESERVED PCIF0 CPU[T/C]2 CPU[T/C]1 CPU[T/C]0 Description LCD_96_100M[T/C] PWRDWN Drive Mode 0 = Driven in PWRDWN, 1 = Tri-state DOT PWRDWN Drive Mode 0 = Driven in PWRDWN, 1 = Tri-state RESERVED, Set = 0 RESERVED, Set = 0 Allow control of PCIF0 with assertion of SW and HW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# Allow control of CPU[T/C]2 with assertion of CPU_STP# 0 = Free running, 1 = Stopped with CPU_STP# Allow control of CPU[T/C]1 with assertion of CPU_STP# 0 = Free running, 1 = Stopped with CPU_STP# Allow control of CPU[T/C]0 with assertion of CPU_STP# 0 = Free running, 1 = Stopped with CPU_STP#
Byte 5: Control Register 5 Bit 7 @Pup 0 Name SRC[T/C] Description SRC[T/C] Stop Drive Mode 0 = Driven when PCI_STP# asserted,1 = Tri-state when PCI_STP# asserted CPU[T/C]2 Stop Drive Mode 0 = Driven when CPU_STP# asserted,1 = Tri-state when CPU_STP# asserted CPU[T/C]1 Stop Drive Mode 0 = Driven when CPU_STP# asserted,1 = Tri-state when CPU_STP# asserted CPU[T/C]0 Stop Drive Mode 0 = Driven when CPU_STP# asserted,1 = Tri-state when CPU_STP# asserted SRC[T/C][9:1] PWRDWN Drive Mode 0 = Driven when PD asserted,1 = Tri-state when PD asserted CPU[T/C]2 PWRDWN Drive Mode 0 = Driven when PD asserted,1 = Tri-state when PD asserted
6
0
CPU[T/C]2
5
0
CPU[T/C]1
4
0
CPU[T/C]0
3 2
0 0
SRC[T/C][9:1] CPU[T/C]2
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Byte 5: Control Register 5 (continued) Bit 1 0 @Pup 0 0 Name CPU[T/C]1 CPU[T/C]0 Description CPU[T/C]1 PWRDWN Drive Mode 0 = Driven when PD asserted,1 = Tri-state when PD asserted CPU[T/C]0 PWRDWN Drive Mode 0 = Driven when PD asserted,1 = Tri-state when PD asserted
Byte 6: Control Register 6 Bit 7 6 5 4 3 @Pup 0 0 1 1 1 Name TEST_SEL TEST_MODE REF1 REF0 REF/N or Tri-state Select 0 = Tri-state, 1 = REF/N Clock Test Clock Mode Entry Control 0 = Normal operation, 1 = REF/N or Tri-state mode, REF1 Output Drive Strength 0 = Low, 1 = High REF0 Output Drive Strength 0 = Low, 1 = High Description
PCI, PCIF and SRC clock SW PCI_STP Function outputs except those set 0=SW PCI_STP assert, 1= SW PCI_STP deassert to free running When this bit is set to 0, all STOPPABLE PCI, PCIF and SRC outputs will be stopped in a synchronous manner with no short pulses. When this bit is set to 1, all STOPPED PCI, PCIF and SRC outputs will resume in a synchronous manner with no short pulses. FSC FSB FSA FSC Reflects the value of the FSC pin sampled on power up 0 = FSC was low during VTT_PWRGD# assertion FSB Reflects the value of the FSB pin sampled on power up 0 = FSB was low during VTT_PWRGD# assertion FSA Reflects the value of the FSA pin sampled on power up 0 = FSA was low during VTT_PWRGD# assertion
2 1 0
HW HW HW
Byte 7: Vendor ID Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 1 1 0 0 0 Name Revision Code Bit 3 Revision Code Bit 2 Revision Code Bit 1 Revision Code Bit 0 Vendor ID Bit 3 Vendor ID Bit 2 Vendor ID Bit 1 Vendor ID Bit 0 Revision Code Bit 3 Revision Code Bit 2 Revision Code Bit 1 Revision Code Bit 0 Vendor ID Bit 3 Vendor ID Bit 2 Vendor ID Bit 1 Vendor ID Bit 0 Description
Byte 8: Control Register 8 Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 1 1 1 Name RESERVED RESERVED RESERVED RESERVED RESERVED USB_48M RESERVED PCIF0 RESERVED, Set = 0 RESERVED, Set = 0 RESERVED, Set = 0 RESERVED, Set = 0 RESERVED, Set = 0 USB_48MHz Output Drive Strength 0= Low, 1= High RESERVED, Set = 1 PCIF0 Output Drive Strength 0 = Low, 1 = High Description
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CY28447
Byte 9: Control Register 9 Bit 7 6 5 4 @Pup 0 0 0 0 Name RESERVED RESERVED S1 S0 Description RESERVED RESERVED 27M_SS / LCD 96_100M SS Spread Spectrum Selection table: S[1:0] SS% `00' = -0.5%(Default value) `01' = -1.0% `10' = -1.5% `11' = -2.0% RESERVED, Set = 1 27M Spread Output Enable 0 = Disable (Tri-state), 1 = Enabled
3 2 1 0
1 1 1 0
RESERVED 27M_SS
27M_SS Spread Enable 27M_SS Spread spectrum enable. 0 = Disable, 1 = Enable. RESERVED RESERVED set = 0
Byte 10: Control Register 10 Bit 7 6 5 4 3 2 1 0 @Pup 1 1 1 1 0 0 0 0 Name RESERVED RESERVED SRC[T/C]9 SRC[T/C]8 RESERVED SRC[T/C]10 SRC[T/C]9 SRC[T/C]8 RESERVED, Set = 1 RESERVED, Set = 1 SRC[T/C]9 Output Enable 0 = Disable (Hi-Z), 1 = Enable SRC[T/C]8 Output Enable 0 = Disable (Hi-Z), 1 = Enable RESERVED, Set = 0 Allow control of SRC[T/C]10 with assertion of SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# Allow control of SRC[T/C]9 with assertion of SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# Allow control of SRC[T/C]8 with assertion of SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# Description
Byte 11: Control Register 11 Bit 7 6 5 4 3 2 1 0 @Pup 0 HW HW HW 0 0 0 HW Name RESERVED RESERVED RESERVED RESERVED 27M_SS / 27M_NSS RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED 27-MHz (spread and non-spread) Output Drive Strength 0 = Low, 1 = High RESERVED RESERVED Set = 0 RESERVED Description
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Byte 12: Control Register 12 Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 0 0 0 Name CLKREQ#9 CLKREQ#8 CLKREQ#7 CLKREQ#6 CLKREQ#5 CLKREQ#4 CLKREQ#3 CLKREQ#2 CLKREQ#9 Input Enable 0 = Disable 1 = Enable CLKREQ#8 Input Enable 0 = Disable 1 = Enable CLKREQ#7 Input Enable 0 = Disable 1 = Enable CLKREQ#6 Input Enable 0 = Disable 1 = Enable CLKREQ#5 Input Enable 0 = Disable 1 = Enable CLKREQ#4 Input Enable 0 = Disable 1 = Enable CLKREQ#3 Input Enable 0 = Disable 1 = Enable CLKREQ#2 Input Enable 0 = Disable 1 = Enable Description
Byte 13: Control Register 13 Bit 7 6 5 4 3 2 1 0 @Pup 0 1 1 1 1 1 1 1 Name CLKREQ#1 LCD 96_100M Clock Speed RESERVED RESERVED PCI4 PCI3 PCI2 PCI1 CLKREQ#1 Input Enable 0 = Disable 1 = Enable LCD 96_100M Clock Speed 0 = 96 MHz 1 = 100 MHz RESERVED, Set = 1 RESERVED, Set = 1 PCI4 (Spread and Non-spread) Output Drive Strength 0 = Low, 1 = High PCI3 (Spread and Non-spread) Output Drive Strength 0 = Low, 1 = High PCI2 (Spread and Non-spread) Output Drive Strength 0 = Low, 1 = High PCI1 (Spread and Non-spread) Output Drive Strength 0 = Low, 1 = High Description
Table 5. Crystal Recommendations Frequency (Fund) 14.31818 MHz Cut AT Loading Load Cap Parallel 20 pF Drive (max.) 0.1 mW Shunt Cap (max.) 5 pF Motional (max.) 0.016 pF Tolerance (max.) 35 ppm Stability (max.) 30 ppm Aging (max.) 5 ppm
The CY28447 requires a Parallel Resonance Crystal. Substituting a series resonance crystal will cause the CY28447 to operate at the wrong frequency and violate the ppm specification. For most applications there is a 300-ppm frequency shift between series and parallel crystals due to incorrect loading.
the crystal will see must be considered to calculate the appropriate capacitive loading (CL). Figure 1 shows a typical crystal configuration using the two trim capacitors. An important clarification for the following discussion is that the trim capacitors are in series with the crystal not parallel. It's a common misconception that load capacitors are in parallel with the crystal and should be approximately equal to the load capacitance of the crystal. This is not true.
Crystal Loading
Crystal loading plays a critical role in achieving low ppm performance. To realize low ppm performance, the total capacitance
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(Ce1,Ce2) should be calculated to provide equal capacitance loading on both sides. Use the following formulas to calculate the trim capacitor values for Ce1 and Ce2. Load Capacitance (each side) Ce = 2 * CL - (Cs + Ci) Total Capacitance (as seen by the crystal) Figure 1. Crystal Capacitive Clarification CLe
=
1 1 ( Ce1 + Cs1 + Ci1 + 1 Ce2 + Cs2 + Ci2
)
Calculating Load Capacitors
In addition to the standard external trim capacitors, trace capacitance and pin capacitance must also be considered to correctly calculate crystal loading. As mentioned previously, the capacitance on each side of the crystal is in series with the crystal. This means the total capacitance on each side of the crystal must be twice the specified crystal load capacitance (CL). While the capacitance on each side of the crystal is in series with the crystal, trim capacitors (Ce1,Ce2) should be calculated to provide equal capacitive loading on both sides.
Clock Chip
CL....................................................Crystal load capacitance CLe......................................... Actual loading seen by crystal using standard value trim capacitors Ce..................................................... External trim capacitors Cs .............................................. Stray capacitance (terraced) Ci ...........................................................Internal capacitance (lead frame, bond wires etc.)
CLK_REQ# Description
The CLKREQ# signals are active LOW inputs used for clean enabling and disabling selected SRC outputs. The outputs controlled by CLKREQ# are determined by the settings in register byte 8. The CLKREQ# signal is a de-bounced signal in that it's state must remain unchanged during two consecutive rising edges of SRCC to be recognized as a valid assertion or deassertion. (The assertion and deassertion of this signal is absolutely asynchronous.) CLK_REQ[1:9]# Assertion (CLKREQ# -> LOW)
Ci1
Ci2 Pin 3 to 6p
Cs1
X1
X2
Cs2 Trace 2.8 pF
XTAL Ce1
Ce2
Trim 33 pF
All differential outputs that were stopped are to resume normal operation in a glitch-free manner. The maximum latency from the assertion to active outputs is between 2 and 6 SRC clock periods (2 clocks are shown) with all SRC outputs resuming simultaneously. All stopped SRC outputs must be driven HIGH within 10 ns of CLKREQ# deassertion to a voltage greater than 200 mV. CLK_REQ[1:9]# Deassertion (CLKREQ# -> HIGH) The impact of deasserting the CLKREQ# pins is that all SRC outputs that are set in the control registers to stoppable via deassertion of CLKREQ# are to be stopped after their next transition. The final state of all stopped DIF signals is LOW, both SRCT clock and SRCC clock outputs will not be driven.
Figure 2. Crystal Loading Example As mentioned previously, the capacitance on each side of the crystal is in series with the crystal. This means the total capacitance on each side of the crystal must be twice the specified load capacitance (CL). While the capacitance on each side of the crystal is in series with the crystal, trim capacitors
CLKREQ#X
SRCT(free running) SRCC(free running) SRCT(stoppable) SRCT(stoppable)
Figure 3. CLK_REQ#[1:9] Deassertion/Assertion Waveform
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PD (Power-down) Clarification The VTT_PWRGD# /PD pin is a dual-function pin. During initial power-up, the pin functions as VTT_PWRGD#. Once VTT_PWRGD# has been sampled LOW by the clock chip, the pin assumes PD functionality. The PD pin is an asynchronous active HIGH input used to shut off all clocks cleanly prior to shutting off power to the device. This signal is synchronized internal to the device prior to powering down the clock synthesizer. PD is also an asynchronous input for powering up the system. When PD is asserted HIGH, all clocks need to be driven to a LOW value and held prior to turning off the VCOs and the crystal oscillator. PD (Power-down) Assertion When PD is sampled HIGH by two consecutive rising edges of CPUC, all single-ended outputs will be held LOW on their next HIGH-to-LOW transition and differential clocks must be held HIGH or tri-stated (depending on the state of the control register drive mode bit) on the next diff clock# HIGH-to-LOW transition within 4 clock periods. When the SMBus PD drive mode bit corresponding to the differential (CPU, SRC, and DOT) clock output of interest is programmed to `0', the clock outputs are held with "Diff clock" pin driven HIGH at 2 x Iref, and "Diff clock#" tri-state. If the control register PD drive mode
PD CPUT, 133MHz CPUC, 133MHz SRCT 100MHz SRCC 100MHz USB, 48MHz DOT96T DOT96C PCI, 33 MHz REF
bit corresponding to the output of interest is programmed to "1", then both the "Diff clock" and the "Diff clock#" are tri-state. Note that Figure 4 shows CPUT = 133 MHz and PD drive mode = `1' for all differential outputs. This diagram and description is applicable to valid CPU frequencies 100, 133, 166, and 200 MHz. In the event that PD mode is desired as the initial power-on state, PD must be asserted HIGH in less than 10 s after asserting Vtt_PwrGd#. It should be noted that 96_100_SSC will follow the DOT waveform is selected for 96 MHz and the SRC waveform when in 100-MHz mode. PD Deassertion The power-up latency is less than 1.8 ms. This is the time from the deassertion of the PD pin or the ramping of the power supply until the time that stable clocks are output from the clock chip. All differential outputs stopped in a three-state condition resulting from power down will be driven high in less than 300 s of PD deassertion to a voltage greater than 200 mV. After the clock chip's internal PLL is powered up and locked, all outputs will be enabled within a few clock cycles of each other. Figure 5 is an example showing the relationship of clocks coming up. It should be noted that 96_100_SSC will follow the DOT waveform is selected for 96 MHz and the SRC waveform when in 100-MHz mode.
Figure 4. Power-down Assertion Timing Waveform
Tstable <1.8 ms
PD CPUT, 133MHz CPUC, 133MHz SRCT 100MHz SRCC 100MHz USB, 48MHz DOT96T DOT96C PCI, 33MHz REF
Tdrive_PWRDN# <300 s, >200 mV
Figure 5. Power-down Deassertion Timing Waveform Rev 1.0, November 20, 2006 Page 11 of 21
CY28447
CPU_STP# Assertion The CPU_STP# signal is an active LOW input used for synchronous stopping and starting the CPU output clocks while the rest of the clock generator continues to function. When the CPU_STP# pin is asserted, all CPU outputs that are set with the SMBus configuration to be stoppable via assertion of CPU_STP# will be stopped within two-six CPU clock periods after being sampled by two rising edges of the internal CPUC clock. The final states of the stopped CPU signals are CPUT = HIGH and CPUC = LOW. There is no change to the output drive current values during the stopped state. The CPUT is driven HIGH with a current value equal to 6 x (Iref), and the CPUC signal will be tri-stated. CPU_STP# Deassertion The deassertion of the CPU_STP# signal will cause all CPU outputs that were stopped to resume normal operation in a synchronous manner, synchronous manner meaning that no short or stretched clock pulses will be produce when the clock resumes. The maximum latency from the deassertion to active outputs is no more than two CPU clock cycles.
CPU_STP#
CPUT CPUC
Figure 6. CPU_STP# Assertion Waveform
CPU_STP# CPUT CPUC CPUT Internal CPUC Internal
Tdrive_CPU_STP#,10 ns>200 mV
Figure 7. CPU_STP# Deassertion Waveform
1.8 ms CPU_STOP# PD CPUT(Free Running CPUC(Free Running CPUT(Stoppable) CPUC(Stoppable)
DOT96T DOT96C
Figure 8. CPU_STP# = Driven, CPU_PD = Driven, DOT_PD = Driven
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1.8mS CPU_STOP# PD CPUT(Free Running) CPUC(Free Running) CPUT(Stoppable) CPUC(Stoppable)
DOT96T DOT96C
Figure 9. CPU_STP# = Tri-state, CPU_PD = Tri-state, DOT_PD = Tri-state PCI_STP# Assertion The PCI_STP# signal is an active LOW input used for synchronous stopping and starting the PCI outputs while the rest of the clock generator continues to function. The set-up time for capturing PCI_STP# going LOW is 10 ns (tSU). (See Figure 10.) The PCIF clocks will not be affected by this pin if their corresponding control bit in the SMBus register is set to allow them to be free running.
Tsu
PCI_STP# PCI_F
PCI SRC 100MHz
Figure 10. PCI_STP# Assertion Waveform
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PCI_STP# Deassertion The deassertion of the PCI_STP# signal will cause all PCI and stoppable PCIF clocks to resume running in a synchronous manner within two PCI clock periods after PCI_STP# transitions to a HIGH level.
Tsu Tdrive_SRC
PCI_STP# PCI_F
PCI SRC 100MHz
Figure 11. PCI_STP# Deassertion Waveform
FS_A, FS_B,FS_C VTT_PW RGD# PW RGD_VRM
VDD Clock Gen Clock State State 0
0.2-0.3mS Delay State 1
W ait for VTT_PW RGD#
Sample Sels State 2 State 3
Device is not affected, VTT_PW RGD# is ignored
Clock Outputs
Off
On
Clock VCO
Off
On
Figure 12. VTT_PWRGD# Timing Diagram
S1
S2 VTT_PWRGD# = Low
Delay >0.25mS
VDD_A = 2.0V
Sample Inputs straps
Wait for <1.8ms S0 S3 VDD_A = off
Power Off
Normal Operation
VTT_PWRGD# = toggle
Enable Outputs
Figure 13. Single-ended Load Configuration
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CY28447
Absolute Maximum Conditions
Parameter VDD VDD_A VIN TS TA TJ OJC OJA ESDHBM UL-94 MSL Description Core Supply Voltage Analog Supply Voltage Input Voltage Temperature, Storage Temperature, Operating Ambient Temperature, Junction Dissipation, Junction to Case Dissipation, Junction to Ambient ESD Protection (Human Body Model) Flammability Rating Moisture Sensitivity Level Relative to VSS Non-functional Functional Functional Mil-STD-883E Method 1012.1 JEDEC (JESD 51) MIL-STD-883, Method 3015 At 1/8 in. Condition Min. -0.5 -0.5 -0.5 -65 0 - - - 2000 V-0 1 Max. 4.6 4.6 VDD + 0.5 150 85 150 20 60 - Unit V V VDC C C C C/W C/W V
Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
DC Electrical Specifications
Parameter All VDDs VILI2C VIHI2C VIL_FS VIH_FS VILFS_C VIMFS_C VIHFS_C VIL VIH IIL IIH VOL VOH IOZ CIN COUT LIN VXIH VXIL IDD3.3V IPD3.3V IPD3.3V Description 3.3V Operating Voltage Input Low Voltage Input High Voltage FS_[A,B] Input Low Voltage FS_[A,B] Input High Voltage FS_C Input Low Voltage FS_C Input Middle Voltage FS_C Input High Voltage 3.3V Input Low Voltage 3.3V Input High Voltage Input Low Leakage Current Input High Leakage Current 3.3V Output Low Voltage 3.3V Output High Voltage High-impedance Output Current Input Pin Capacitance Output Pin Capacitance Pin Inductance Xin High Voltage Xin Low Voltage Dynamic Supply Current Power-down Supply Current Power-down Supply Current At max. load in low drive mode per Figure 15 and Figure 17 @133 MHz PD asserted, Outputs Driven PD asserted, Outputs Tri-state Except internal pull-up resistors, 0 < VIN < VDD Except internal pull-down resistors, 0 < VIN < VDD IOL = 1 mA IOH = -1 mA 3.3 5% SDATA, SCLK SDATA, SCLK Condition Min. 3.135 - 2.2 VSS - 0.3 0.7 VSS - 0.3 0.7 1.8 VSS - 0.3 2.0 -5 - - 2.4 -10 3 3 - 0.7VDD 0 - - - Max. 3.465 1.0 - 0.35 VDD + 0.5 0.35 1.7 VDD + 0.5 0.8 VDD + 0.3 5 5 0.4 - 10 5 6 7 VDD 0.3VDD 300 70 5 Unit V V V V V V V V V V A A V V A pF pF nH V V mA mA mA
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AC Electrical Specifications
Parameter Crystal TDC XIN Duty Cycle The device will operate reliably with input duty cycles up to 30/70 but the REF clock duty cycle will not be within specification When XIN is driven from an external clock source Measured between 0.3VDD and 0.7VDD As an average over 1-s duration Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX 47.5 52.5 % Description Condition Min. Max. Unit
TPERIOD T R / TF TCCJ LACC CPU at 0.7V TDC TPERIOD TPERIOD TPERIOD TPERIOD TPERIODSS TPERIODSS TPERIODSS TPERIODSS TPERIODAbs TPERIODAbs TPERIODAbs TPERIODAbs
XIN Period XIN Rise and Fall Times XIN Cycle to Cycle Jitter Long-term Accuracy CPUT and CPUC Duty Cycle 100-MHz CPUT and CPUC Period 133-MHz CPUT and CPUC Period 166-MHz CPUT and CPUC Period 200-MHz CPUT and CPUC Period
69.841 - - - 45 9.997001 7.497751 5.998201 4.998500 9.997001 7.497751 5.998201 4.998500 9.912001 7.412751 5.913201 4.913500 9.912001 7.412751 5.913201 4.913500 - - - - - 175 - - -
71.0 10.0 500 300 55 10.00300 7.502251 6.001801 5.001500 10.05327 7.539950 6.031960 5.026634 10.08800 7.587251 6.086801 5.086500 10.13827 7.624950 6.116960 5.111634 85[2] 125[2] 300 100 150 700 20 125 125
ns ns ps ppm % ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ps ps ppm ps ps ps % ps ps
100-MHz CPUT and CPUC Period, SSC Measured at crossing point VOX 133-MHz CPUT and CPUC Period, SSC Measured at crossing point VOX 166-MHz CPUT and CPUC Period, SSC Measured at crossing point VOX 200-MHz CPUT and CPUC Period, SSC Measured at crossing point VOX 100-MHz CPUT and CPUC Absolute period 133-MHz CPUT and CPUC Absolute period 166-MHz CPUT and CPUC Absolute period 200-MHz CPUT and CPUC Absolute period Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured from VOL = 0.175 to VOH = 0.525V Determined as a fraction of 2*(TR - TF)/(TR + TF)
TPERIODSSAbs 100-MHz CPUT and CPUC Absolute period, SSC TPERIODSSAbs 133-MHz CPUT and CPUC Absolute period, SSC TPERIODSSAbs 166-MHz CPUT and CPUC Absolute period, SSC TPERIODSSAbs 200-MHz CPUT and CPUC Absolute period, SSC TCCJ TCCJ2 LACC TSKEW TSKEW2 T R / TF TRFM TR TF CPUT/C Cycle to Cycle Jitter CPU2_ITP Cycle to Cycle Jitter Long-term Accuracy CPU1 to CPU0 Clock Skew CPU2_ITP to CPU0 Clock Skew CPUT and CPUC Rise and Fall Time Rise/Fall Matching Rise Time Variation Fall Time Variation
Note: 2. Measured with one REF on.
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AC Electrical Specifications (continued)
Parameter VHIGH VLOW VOX VOVS VUDS VRB SRC at 0.7V TDC TPERIOD TPERIODSS TPERIODAbs SRCT and SRCC Duty Cycle 100-MHz SRCT and SRCC Period 100-MHz SRCT and SRCC Absolute Period Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured from VOL = 0.175 to VOH = 0.525V Determined as a fraction of 2*(TR - TF)/(TR + TF) 45 9.997001 9.997001 9.872001 9.872001 - - - 175 - - - Math averages Figure 17 Math averages Figure 17 660 -150 180 - -0.3 See Figure 17. Measure SE Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX - 45 9.997001 9.997001 9.872001 9.872001 10.41354 10.41354 10.16354 10.16354 - - 55 10.00300 10.05327 10.12800 10.17827 250 125[2] 300 800 20 125 125 850 - 550 VHIGH + 0.3 - 0.2 55 10.00300 10.05327 10.12800 10.17827 10.41979 10.47215 10.66979 10.72266 125 300 % ns ns ns ns ps ps ppm ps % ps ps mV mV mV V V V % ns ns ns ns ns ns ns ns ps ppm Voltage High Voltage Low Crossing Point Voltage at 0.7V Swing Maximum Overshoot Voltage Minimum Undershoot Voltage Ring Back Voltage See Figure 17. Measure SE Description Condition Math averages Figure 17 Math averages Figure 17 Min. 660 -150 250 - -0.3 - Max. 850 - 550 VHIGH + 0.3 - 0.2 Unit mV mV mV V V V
100-MHz SRCT and SRCC Period, SSC Measured at crossing point VOX
TPERIODSSAbs 100-MHz SRCT and SRCC Absolute Period, SSC TSKEW TCCJ LACC T R / TF TRFM TR TF VHIGH VLOW VOX VOVS VUDS VRB TDC TPERIOD TPERIODSS TPERIODAbs Any SRCT/C to SRCT/C Clock Skew SRCT/C Cycle to Cycle Jitter SRCT/C Long Term Accuracy SRCT and SRCC Rise and Fall Time Rise/Fall Matching Rise TimeVariation Fall Time Variation Voltage High Voltage Low Crossing Point Voltage at 0.7V Swing Maximum Overshoot Voltage Minimum Undershoot Voltage Ring Back Voltage SSCT and SSCC Duty Cycle 100-MHz SSCT and SSCC Period 100-MHz SSCT and SSCC Absolute Period
LCD 96_100M_SSC at 0.7V
100-MHz SSCT and SSCC Period, SSC Measured at crossing point VOX
TPERIODSSAbs 100-MHz SRCT and SRCC Absolute Period, SSC TPERIOD TPERIODSS TPERIODAbs 96-MHz SSCT and SSCC Period 96-MHz SSCT and SSCC Absolute Period
96-MHz SSCT and SSCC Period, SSC Measured at crossing point VOX
TPERIODSSAbs 96-MHz SRCT and SRCC Absolute Period, SSC TCCJ LACC SSCT/C Cycle to Cycle Jitter SSCT/C Long Term Accuracy
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CY28447
AC Electrical Specifications (continued)
Parameter T R / TF TRFM TR TF VHIGH VLOW VOX VOVS VUDS VRB TDC TPERIOD TPERIODSS TPERIODAbs THIGH TLOW T R / TF TSKEW TCCJ LACC DOT96 at 0.7V TDC TPERIOD TPERIODAbs TCCJ LACC T R / TF TRFM TR TF VHIGH VLOW VOX VOVS VUDS VRB 48_M at 3.3V TDC Duty Cycle Measurement at 1.5V 45 55 % DOT96T and DOT96C Duty Cycle DOT96T and DOT96C Period DOT96T/C Cycle to Cycle Jitter DOT96T/C Long Term Accuracy DOT96T and DOT96C Rise and Fall Time Rise/Fall Matching Rise Time Variation Fall Time Variation Voltage High Voltage Low Crossing Point Voltage at 0.7V Swing Maximum Overshoot Voltage Minimum Undershoot Voltage Ring Back Voltage See Figure 17. Measure SE Math averages Figure 17 Math averages Figure 17 Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured from VOL = 0.175 to VOH = 0.525V Determined as a fraction of 2*(TR - TF)/(TR + TF) 45 10.41354 10.16354 - - 175 - - - 660 -150 250 - -0.3 - 55 10.41979 10.66979 250 300 900 20 125 125 850 - 550 VHIGH + 0.3 - 0.2 % ns ns ps ppm ps % ps ps mV mV mV V V V Description SSCT and SSCC Rise and Fall Time Rise/Fall Matching Rise TimeVariation Fall Time Variation Voltage High Voltage Low Crossing Point Voltage at 0.7V Swing Maximum Overshoot Voltage Minimum Undershoot Voltage Ring Back Voltage PCI Duty Cycle Spread Disabled PCIF/PCI Period Spread Disabled PCIF/PCI Period PCIF and PCI high time PCIF and PCI low time PCIF/PCI rising and falling Edge Rate Any PCI clock to Any PCI clock Skew PCIF and PCI Cycle to Cycle Jitter PCIF/PCI Long Term Accuracy See Figure 17. Measure SE Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 2.4V Measurement at 0.4V Measured between 0.8V and 2.0V Measurement at 1.5V Measurement at 1.5V Measured at crossing point VOX Math averages Figure 17 Math averages Figure 17 Condition Measured from VOL = 0.175 to VOH = 0.525V Determined as a fraction of 2*(TR - TF)/(TR + TF) Min. 175 - - - 660 -150 250 - -0.3 - 45 29.99100 29.9910 29.49100 29.49100 12.0 12.0 1.0 - - - Max. 700 20 125 125 850 - 550 VHIGH + 0.3 - 0.2 55 30.00900 30.15980 30.50900 30.65980 - - 4.0 500 500 300 Unit ps % ps ps mV mV mV V V V % ns ns ns ns ns ns V/ns ps ps ppm
PCI/PCIF at 3.3V
Spread Enabled PCIF/PCI Period, SSC Measurement at 1.5V
TPERIODSSAbs Spread Enabled PCIF/PCI Period, SSC Measurement at 1.5V
DOT96T and DOT96C Absolute Period Measured at crossing point VOX
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CY28447
AC Electrical Specifications (continued)
Parameter TPERIOD TPERIODAbs THIGH TLOW T R / TF TCCJ LACC 27_M at 3.3V TDC TPERIOD THIGH TLOW T R / TF TCCJ LACC REF at 3.3V TDC TPERIOD TPERIODAbs T R / TF TSKEW TCCJ LACC TSTABLE TSS TSH REF Duty Cycle REF Period REF Absolute Period REF Rising and Falling Edge Rate REF Clock to REF Clock REF Cycle to Cycle Jitter Long Term Accuracy Clock Stabilization from Power-up Stopclock Set-up Time Stopclock Hold Time Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measured between 0.8V and 2.0V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V 45 69.8203 68.82033 1.0 - - - - 10.0 0 55 69.8622 70.86224 4.0 500 1000 300 1.8 - - % ns ns V/ns ps ps ppm ms ns ns Duty Cycle Spread Disabled 27M Period Spread Enabled 27M Period 27_M High time 27_M Low time Rising and Falling Edge Rate Cycle to Cycle Jitter 27_M Long Term Accuracy Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 2.0V Measurement at 0.8V Measured between 0.8V and 2.0V Measurement at 1.5V Measured at crossing point VOX 45 27.000 27.000 10.5 10.5 1.0 - - 55 27.0547 27.0547 - - 4.0 500 0 ns ns V/ns ps ppm % ns Period Absolute Period 48_M High time 48_M Low time Rising and Falling Edge Rate Cycle to Cycle Jitter 48M Long Term Accuracy Description Condition Measurement at 1.5V Measurement at 1.5V Measurement at 2.4V Measurement at 0.4V Measured between 0.8V and 2.0V Measurement at 1.5V Measured at crossing point VOX Min. 20.83125 20.48125 8.094 7.694 1.0 - - Max. 20.83542 21.18542 11.100 11.100 2.0 350 100 Unit ns ns ns ns V/ns ps ppm
ENABLE/DISABLE and SET-UP
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CY28447
Test and Measurement Set-up
For Single-ended Signals and Reference The following diagram shows test load configurations for the single-ended PCI, USB, and REF output signals.
PCI/ USB
33 60
Measurement Point
5pF
12 60
Measurement Point
5pF
REF
12 60
Measurement Point
5pF
Figure 15.Single-ended Load Configuration Low Drive Option
12 60
M easurem ent P oint
5pF
P C I/ USB
12 60
M easurem ent P oint
5pF
12 60
M easurem ent P oint
5pF
REF
12 60 12 60
M easurem ent P oint
5pF
M easurem ent P oint
5pF
Figure 16. Single-ended Load Configuration High Drive Option The following diagram shows the test load configuration for the differential CPU and SRC outputs.
33 4 9 .9 33 4 9 .9
1 0 0 D if f e r e n t ia l
CPUT SRCT D O T96T 96_100_SSC T CPUC SRCC D O T96C 96_100_SSC C IR E F 475
M e a s u re m e n t P o in t
2pF
M e a s u re m e n t P o in t
2pF
Figure 17. 0.7V Differential Load Configuration
Rev 1.0, November 20, 2006
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CY28447
3 .3 V s ig n a l s
T DC
-
3 .3 V
2 .4 V
1 .5 V
0 .4 V 0V
TR
TF
Figure 18. Single-ended Output Signals (for AC Parameters Measurement)
Ordering Information
Part Number Lead-free CY28447LFXC CY28447LFXCT 72-pin QFN 72-pin QFN - Tape and Reel Commercial, 0 to 85C Commercial, 0 to 85C Package Type Product Flow
Package Diagram
72-Lead QFN 10 x 10 mm (Punch Version) LF72A
While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for the use of any circuitry or for the infringement of any patents or other rights of third parties which would result from each use. This product is intended for use in normal commercial applications and is not warranted nor is it intended for use in life support, critical medical instruments, or any other application requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursuant to additional processing by Spectra Linear Inc., and expressed written agreement by Spectra Linear Inc. Spectra Linear Inc. reserves the right to change any circuitry or specification without notice.
Rev 1.0, November 20, 2006
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